1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly, to a liquid crystal display panel and a fabricating method thereof for reducing the number of mask processes as well as preventing a corrosion of a shorting line.
2. Description of the Related Art
In general, a liquid crystal display (LCD) drives a liquid crystal by an electric field formed between a pixel electrode and a common electrode arranged opposite from each other on upper and lower substrates. The LCD controls the application of the electric field across a liquid crystal, and accordingly light transmittance of the liquid crystal, thereby displaying a desired picture.
The LCD includes a thin film transistor array substrate structure and a color filter array substrate that are joined opposite from each other, a spacer for constantly keeping a cell gap between the two substrates, and a liquid crystal filled in the cell gap. The thin film transistor substrate structure comprises of a plurality of signal wirings and thin film transistors, and an alignment film coated thereon for the aligning the liquid crystal. The color filter array substrate structure is comprised of a color filter for implementing a color, a black matrix for preventing a light leakage, and an alignment film coated thereon for alignment of the liquid crystal.
In such a LCD, the thin film transistor substrate structure has a complicated fabrication process involving a semiconductor process that requires a plurality of mask processes. These processes lead to a significantly increased in the manufacturing cost of the liquid crystal display panel. To solve this, a thin film transistor array substrate structure has been developed with a reduced number of mask processes. Since one mask process can accommodate several processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection processes, etc., the total number of mask processes can be reduced. Recently, a four-round mask process, one less mask process from the existent five-round mask process is becoming a standard mask process of the thin film transistor.
FIG. 1 is a plan view illustrating a related art lower transistor array substrate adopting a four-round mask process, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate structure taken along line II–II′ of FIG. 1. Referring to FIGS. 1 and 2, the thin film transistor array substrate structure includes a gate line 2 and a data line 4 provided on a lower substrate 1 intersecting each other and having a gate insulating pattern 12 therebetween. The gate line 2 is provided to apply a gate signal and the data line 4 is provided to a data signal at an intersection structure to define a pixel area 5. Furthermore, the thin film transistor array substrate includes a thin film transistor 30 provided at each intersection, a pixel electrode 22 provided at a cell area defined by an intersection, a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.
The thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. The thin film transistor 30 allows a pixel signal on the data line 4 to be charged and maintained at the pixel electrode 22 in response to a gate signal from the gate line 2. Further, the thin film transistor 30 includes an active layer 14 overlapping the gate electrode 6 having a gate insulating pattern 12 therebetween to define a channel between the source electrode 8 and the drain electrode 10.
The active layer 14 also overlaps the data line 4 and a lower data pad electrode 62. On the active layer 14, an ohmic contract layer 16 is provided for making a contact with the data line 4, the source electrode 8, with the drain electrode 10 and the lower data pad electrode 62. The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 via a first contact hole 20 passing through a protective film 18 and is provided at a pixel area 5.
Thus, an electric field is formed between the pixel electrode 22 to which a pixel signal is supplied via the thin film transistor 30 and a common electrode (not shown) supplied with a reference voltage. Liquid crystal molecules between the thin film transistor array substrate structure and the color filter array substrate structure rotates due to a dielectric anisotropy induced by such an electric field. Transmittance of a light onto the pixel area 5 is varied depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.
The gate pad 50 is connected to a gate driver (not shown) to apply a gate signal to the gate line 2. The gate pad 50 consists of a lower gate pad electrode 52 extended from the gate line 2, and an upper gate pad electrode 54 connected to the lower gate pad electrode 52 via a second contact hole 56 passing through the gate insulating pattern 12 and the protective film 18.
The data pad 60 is connected to a data driver (not shown) to apply a data signal to the data line 4. The data pad 60 comprises a lower data pad electrode 62 extended from the data line 4, and an upper data pad electrode 64 connected to an upper data pad electrode 64 connected to the lower data pad electrode 62 via a third contact hole 66 passing through the protective film 18.
Hereinafter, a method of fabricating the thin film transistor array substrate structure having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3D. Referring to FIG. 3A, a first conductive pattern group including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52 are provided on the lower substrate 1 by the first mask process. More specifically, a gate metal film is formed on the lower substrate 1 by a deposition technique such as sputtering. Then, the gate metal film is patterned by photolithography and etching process using a first mask to form the first conductive pattern group including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52. The gate metal film is made from an aluminum group metal, and the like.
Referring to FIG. 3B, the gate insulating pattern 12 is coated over the lower substrate 1 provided with the first conductive pattern group. Further, semiconductor pattern including the active layer 14 and the ohmic contact layer 16; and a second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, and the lower data pad electrode 62 are formed on the gate insulating pattern 12 by the second mask process.
More specifically, a plurality of layers are sequentially provided on the lower substrate 1. The gate insulating pattern 12, an amorphous silicon layer, a n+ amorphous silicon layer, and a data metal layer are sequentially disposed on the lower substrate 1 provided with the first conductive pattern group formed by the deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc. Herein, the gate insulating pattern 12 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The data metal layer is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the data metal layer by photolithography using a second mask process. In this process, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion. Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to provide the second conductive pattern group including the data line 4, the source electrode 8, and the drain electrode 10 which is integral to the source electrode 8.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned simultaneously by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer 16 and the active layer 14. The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal layer and the ohmic contact layer 16 of the channel portion are etched by the dry etching process. The active layer 14 of the channel portion is exposed to disconnect the source electrode 8 from the drain electrode 10. Then, the photo-resist pattern left on the second conductive pattern group is removed by the stripping process.
Referring to FIG. 3C, the protective film 18 including the first to third contact holes 20, 56 and 66 are formed on the gate insulating pattern 12 provided with the second conductive pattern group. The protective film 18 is entirely formed on the gate insulating pattern 12 by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 18 is patterned by the photolithography and the etching process using a third mask to define the first to third contact holes 20, 56 and 66. The first contact hole 20 passes through the protective film 18 to expose the drain electrode 10, whereas the second contact hole 56 passes through the protective film 18 and the gate insulating pattern 12 to expose the lower gate pad electrode 52. The third contact hole 66 passes through the protective film 18 to expose the lower gate pad electrode 52. Herein, when a metal having a large dry etching ratio, such as molybdenum (Mo), is used as the data metal layer, the first and third contact holes 20 and 66 pass through the drain electrode 10 and the lower data pad electrode 62, respectively, to expose the side surfaces thereof. The protective film 18 is made from an inorganic insulating material identical to the gate insulating pattern 12, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, the third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 54, and the upper data pad electrode 64 are provided on the protective film 18 by the fourth mask process. More specifically, a transparent conductive film is coated onto the protective film 18 by a deposition technique such as the sputtering, etc. Then, the transparent conductive film is patterned by the photolithography and the etching process using a fourth mask to provide the third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 54, and the upper data pad electrode 64. The pixel electrode 22 is electrically connected to the drain electrode 10 via the first contact hole 20. The upper gate pad electrode 54 is electrically connected to the lower gate pad electrode 52 via the second contact hole 56. The upper data pad electrode 64 is electrically connected to the lower data pad electrode 62, via the third contact hole 66. The transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO) or indium-zinc-oxide (IZO).
As described above, the related art thin film transistor array substrate structure and the fabricating method thereof adopts the four-round mask process, thereby reducing the total number of fabricating processes and hence reducing a manufacturing cost proportional to the fabrication with the five-round mask process. However, since the four-round mask process still has a complicate fabricating process to limit the cost reduction, there has been required a scheme capable of more simplifying the fabricating process to further reduce the manufacturing cost.
Furthermore, as shown in FIG. 4A, the thin film transistor array substrate structure of the related art liquid crystal display panel includes a gate shorting bar 80 connected to the gate pad 50 via a gate shorting line 82, and a data shorting bar 90 connected to the data pad 60 via a data shorting line 92. This feature is included to conduct a quality check to inspect a short and a breakage of the signal line after it was provided by the four-round mask process. As shown in FIG. 4B, when the lower substrate 1 is taken along the scribing line SCL (line crossing through the gate shorting line 82 and the data shorting line 92) after a poor performance of the liquid crystal display panel was detected by the shorting bars 80 and 90, then the gate shorting line 82 and the data shorting line 92 would have been exposed along the side surface of the lower substrate 1. In this case, a metal possessing a poor corrosion resistance, for example, the gate shorting line 82 formed from aluminum or copper, etc. becomes liable for a metal corrosion at a high temperature and in a humid environment. In addition, application of an electric field for driving of the TFT can cause the metal corrosion. These corrosion phenomenon can cause further problems such that the metal corrosion can extend into the gate pad 50 and the data pad 60 as well as the gate line 2 and the data line 4 when given sufficient time.